Problem

The semiconductor industry faces a growing sustainability and cost challenge with the increasing reliance on large language models (LLMs) for AI-assisted hardware design. LLM inference demands substantial computational resources and energy, leading to high operational expenses. While LLMs offer productivity gains, their power consumption exacerbates the industry's existing energy burden. This paper questions whether large, "Goliath-sized" models are always necessary, proposing that smaller, more efficient "David-sized" models could be viable alternatives if properly utilized. Current research either evaluates SLMs in single-shot settings with poor results or uses sophisticated multi-agent systems exclusively with expensive LLMs, leaving a gap in understanding SLM potential within agentic frameworks for hardware design.

Method

The authors developed a novel heterogeneous agentic AI framework specifically optimized for small language models (SLMs) in hardware design automation. This framework mimics the mentorship structure a junior engineer receives from a senior, providing context preparation, structured instructions, curated examples, iterative validation, and targeted feedback. It comprises five cooperating agents: a Planning and Pre-processing Agent for context retrieval and task decomposition, an SLM-aware Prompt Engineering Agent for structuring prompts with keywords and examples while managing token budget, a CodeGen Agent for reasoning-guided Verilog generation, a Validation Agent (syntax, I/O port usage, CocoTB tests), and an Adaptive Feedback Agent for error categorization, quality scoring, and contextual error gathering. This closed-loop pipeline iterates up to five rounds, refining code until checks pass or limits are met, enabling SLMs to produce high-quality RTL. The evaluation was conducted on the NVIDIA Comprehensive Verilog Design Problems (CVDP) benchmark, focusing on Non-Agentic Code Generation and Code Comprehension tasks, using various SLMs (e.g., SmolLM2, DeepSeek-R1, Granite-4, Phi-3.5-mini-instruct) and GPT-o4-mini as an LLM baseline.

Results

The experiments showed significant gains for SLMs when coupled with the agentic framework, particularly in code generation tasks. For the `cid007` category, SLMs like DeepSeek-R1 and Granite-4 demonstrated substantial improvements (30-140% relative improvement), with some even surpassing the performance of GPT-o4-mini. The agentic framework effectively reduced syntactic errors and improved functional correctness. In code comprehension tasks, SLMs exhibited strong performance, with models like Phi-3.5-mini-instruct and DeepSeek-R1 achieving accuracy comparable to or even exceeding LLMs in higher-level reasoning and structured code reconstruction tasks. This indicates that SLMs, when guided by strategic agentic processes, can offer favorable accuracy-efficiency trade-offs without sacrificing solution quality for specific hardware design tasks.

Implications

The findings suggest that "strategy over scale" is a viable and powerful approach for AI-assisted hardware design. By leveraging well-designed agentic frameworks, compact and energy-efficient small language models can achieve practical performance levels on tasks traditionally thought to require large, expensive models. This paves the way for more sustainable and cost-effective AI solutions in the semiconductor industry, reducing the environmental footprint and operational expenses associated with LLM inference. The work encourages further research into task-specific SLMs combined with agentic pipelines and supports the development of open-source frameworks for efficient AI-assisted hardware design.